In the field of semiconductor device manufacturing, active semiconductor devices such as, for example, transistors are generally manufactured or fabricated through processes commonly known as front end of line (FEOL) technologies. A transistor may be, for example, a field-effect-transistor (FET) and may be more specifically a complementary metal-oxide-semiconductor (CMOS) FET. A FET may further be a PFET doped with p-type dopant or an NFET doped with n-type dopant. Recently, high-k metal gate (HKMG) semiconductor transistors have been widely adopted because of their superior performance over conventional poly-based CMOS-FET. In addition, a replacement metal gate (RMG) process has been developed for manufacturing HKMG transistors with further enhanced performance.
It is generally known that performance of a transistor may be greatly improved by introducing stresses in the channel region of the transistor. This is mainly because stresses increase the mobility of carriers, either holes or electrons depending on the type (n-type or p-type) of the transistor, thereby increasing the response speed of the transistor. There are many different approaches of applying stresses to the channel region of a transistor. For example, appropriate types of stressors may be formed to be embedded in the source and drain regions of a transistor that apply stresses toward the channel region in-between the source and drain regions.
In forming source and drain with embedded stressors, recesses are normally first created in the source and drain regions, which is then followed by epitaxial growth of stressor making materials, such as silicon-germanium (SiGe) for PFET transistors and silicon-carbide (SiC) for NFET transistors, in the created recess regions. The embedded epitaxial material, such as SiGe or SiC, has a lattice constant that is designed to be different from that of silicon substrate. Using silicon substrate as a template, the embedded stressor materials growing with different lattice constant generate stresses, compressive or tensile, to surrounding regions including the channel region of transistors.
In a conventional process of forming recesses, for example, a hard-mask is first formed to cover both gate and source/drain region of a transistor. Portions of the hard-mask in the source/drain regions are subsequently etched away or removed through a directional etching process to expose underneath source/drain regions in order to create openings therein for forming the recesses. Recesses are next created or etched in the source/drain regions. Generally, recesses thus formed are separated from the gate of transistor by an additional distance attributed to the thickness of hard-mask remaining at the sidewalls of the gate.
Furthermore, due to the need of forming different types of stressors for different types of transistors on a same substrate, additional hard-mask layers and thus additional distances may be added to the space between the gate (and channel region underneath) and the recesses being created when each time such different stressors are formed. The added distances between the gate and the recesses further weaken the effectiveness of stressors, which are epitaxially formed inside the recesses. That negatively impacts the mobility of the charge carriers. Moreover, it counters the trend of continuous scaling down in real estate for manufacturing semiconductor devices, where real estate for source/drain regions is increasingly becoming smaller and/or narrower.